How do SPMT-enabled memories reduce system cost?
Device manufacturers are faced with the challenge and expense of adding more processors to deliver increased functionality to support media-rich applications and content demanded by consumers. This requires faster and denser memory, which tends to drive up both power consumption and system cost. Shifting from parallel memory technology to SPMT-enabled memory reduces system cost as follows: • Reduced pin count translates to a potentially significant per-unit cost reduction. For example, using 40 fewer pins at a cost of one cent per pin lowers system cost by 40 cents. Multiply these 40 cents by the number of units sold and the cost savings add up. • SPMT-enabled memory consumes about half as much power as standard parallel memories. Reduced power consumption means that manufacturers can opt for smaller, cheaper batteries without sacrificing system run time. • Simplified circuit board layouts with fewer parts are both easier and cheaper to design and manufacture. Simplicity is achieved be
