How do Power Macintosh computers provide continuous refreshing?
The power source and refreshing are provided as long as the computer is powered on. The Memory Controller in Apple Macintosh and Power Macintosh computers generate a CAS (Columb Address Strobe) before RAS (Row Address Strobe) refresh cycle every 15.6 msec. DRAM devices contain an address refresh counter which is triggered by a CAS before RAS memory cycle. A 16 MBit (11/11) device with an 11 row address – referred to as a 2K refresh part – requires all row address combinations (2048) to be accessed every 32 msec. A 4K refresh device (12/10) requires 64 msec to refresh all row addresses. DRAM row addresses are refreshed by the Refresh Address Counter, which is triggered by a CAS before RAS refresh cycle. The importance, therefore, lies less in whether or not a Macintosh CPU supports 1K, 2K, and/or 4K refresh DRAM parts than whether the Macintosh Memory Controller and DRAM devices have compatible addressing schemes, and whether the DRAM devices are compatible with CAS before RAS refresh c
