How do I instantiate the supplied EDIF netlist into my design?
Files are supplied with the core, illustrating how to instance the cores in a higher level VHDL or Verilog design. You may give the core entity any name you like, but you must ensure the netlist for the core has the same name. It is assumed that a synthesis tool will take care of adding ipads and ibufs to the primary inputs and obufs and opads to the primary outputs. The “reset” signal should be driven onto the GSR (Global Set Reset) net and the “clk” signal onto a global clock net. Most synthesis tools have a command to allow this to be specified. If not, it can be done explicitly by instancing a “startup” and a “bufg” component. This is explained in the Xilinx on-line documentation. Synthesis tools should treat the core as a black box. You may need to set some option, such as “don’t touch”, depending on your synthesis tool. If you use a schematic editor then you must create a symbol either manually or automatically, if your design entry system has an HDL component to symbol conversio
