How do I disable the L2 cache on an Intel 430HX PCIset design?
For power management, some designers may want to disable the cache from the Intel 430HX PCIset. Current documentation does not describe disabling cache or related chip select status. To disable the L2 cache from the Intel 430HX PCIset, clear the following bits: SCS (Cache Control Register, Bits[7:6]: Secondary Cache Size) = 00 FLCE(Cache Control Register, Bit 0: First Level Cache Enable) = 0 ECE (Cache Control Register, Bit 2: Extended Cacheability Enable) = 0 SCFMI (Cache Control Register, Bit 1: Secondary Cache Force Miss or Invalidate) = 0 See the Intel 430HX PCIset datasheet for further description of these bits. If chip selects are asserted, the SRAM device would be selected and the power down state would be exited. The chip select lines will still be active even when L2 is turned off. Therefore, this may not work well with the power down mode on the SRAMs for a desktop design.
