How different is the Elastix design flow from the classical ASIC design flows?
The Elastix design flow starts from a classical design flow in which few minor adjustments are added. Even though elasticity can be introduced at various levels of the flow, usually this happens after placement has been performed. Up to that point, the circuit is still genuinely synchronous. The circuit is then de-synchronized by simple ECO transformations. Initially, some latches are added in the logic to make the data flow elastic. Next, the clock trees are synthesized. Finally, some elastic controllers are added to generate the Elastic Clocks that will be connected to the clock trees. After de-synchronization, the physical layout is synthesized using conventional EDA flows. Along this process, the classical timing constraints are substituted by another set of equivalent constraints related to the Elastic Clocks. These constraints are preserved until timing sign-off. Therefore, the Elastix design flow uses the same EDA tools as a conventional design flow (RTL synthesis, clock tree sy
