How can VeloceRF minimize IC development cycles and costs?
In several ways. First of all, the sheer speed in producing inductor models for complex layouts eliminates the wait usually associated with EM tools. Rapid re-spins of a design in the schematic or post-layout phase are thus made possible. Human error is avoided, since inductor modeling is now part of the physical design flow and there is no need for transferring and stitching models from external simulators. Additionally, since VeloceRF does not require trimming or parameter fitting on measured data, you can design with inductors directly for first-pass success, eliminating the delays and costs of running testchips with inductor “libraries” for characterization and re-use.
