How can the DC offset seen at the load be reduced to eliminate clicks and pops at turn on/off?
The DC offset seen at the load is due to the duty cycle error. When there is no input signal present the class D amplifier should show a 50% duty cycle square wave. Any error from exactly 50% creates some DC offset at the load. To minimize the DC offset the ratio of Rf/R2 should be above 100. A higher ratio will give a lower DC offset. If the DC offset is still unacceptable then adjusting the value of the resistor labeled ROFFSET shown in the Application Circuit in the Data Sheet (Figure 1, page4) will reduce the DC offset to 0V. This resistor puts a small DC voltage at the input so there is no duty cycle error. The value of this resistor will often be very large, several mega – ohms.
