How can I quickly create irsim test vectors?
A very common way to create irsim test vectors is to use Verilog. Which makes sense, since you are using that tool already to verify your RTL code. Now if you create irsim vectors from that testbench then you can verify your circuit with the same vectors as the RTL code. The big advantage of irsim is that it automatically checks the output and flags an error if it does not see the expected result. That way you can run large test sets e.g. over night and in the morning irsim will report which vectors, if any, have failed. Here is an example that creates testvectors for a 32-bit adders. This is simple because we can use the “+” operator to compute the expected result. With a larger circuit you will need to use your RTL code to produce the expected result. Once we have all the data we just write it into a text file. module vecgen; reg [32:1] a; reg [32:1] b; reg c; reg [32:1] s; integer vecfile; integer i; initial begin vecfile = $fopen(“testbench.cmd”); for(i=0;i<1000;i=i+1) begin a=$ran
