How are differential pairs handled in Xilinx Devices?
On Xilinx Devices, when you specify an pin as a differential, the scan cells on the N side get disconnected from the I/O and all differential traffic is monitored from the P side scan cells. The N-Side scan cells are still there, and you can still see (and put values in) the N side scan cells, but they don’t do anything. This all applies to post configuration. Pre configuration you have total control over all scan cells.
