How are back-to-back burst accesses between a single bank and a two-bank SRAM cache solution performed when using an Intel 430TX PCIset?
To implement a two-bank solution in cache when performing back-to-back burst accesses, it is necessary to incur a one-clock cycle delay over a single bank solution. This ensures that one bank does not power-down before all data is driven out. For example, if using two banks of cache, when the seam is crossed from bank one to bank two, the J HA18 line (that feeds into CE2 or CE2# of the SRAM) will toggle. During this time, bank one valid data is still being driven out of the SRAM while the J HA18 line changes, and ADSP# on the SRAM (ADSC from the host) is active. The bank one SRAM interprets this disabling of chip enable as a request to enter a low power mode, and the current data will be lost. To prevent losing the current data, the CCS# pin from the chipset (attached to CE# on the SRAM) must be negated. When negated, the ADSP# on the SRAM is ignored and the device will wait to sample the new address until the CADS# signal from the chipset (ADSC# on the SRAM) is active. At this time, t
