How accurately does the Verilog model predict the behavior of the PLL? A: The Verilog model is very close but not perfect.
• In steady state, the Verilog model does not model any jitter that might be present in the real PLL. • During startup, the Verilog model will achieve lock much more quickly than the actual PLL to speed up Verilog simulations. The PLL specifications list the correct time required to achieve lock. • The number of cycles required by the verilog model for relock, after a clock source or runtime divider changes, is also less than the actual PLL. • After the PLL reset has been de-asserted, the PLL will proceed towards a “locked” state. During this transition from a low reset frequency to a higher operating frequency, the PLL output a few cycles that are higher then the final target frequency. The PLL specifications list the maximum overshoot level. The Verilog model may exhibit somewhat different behavior during this “locking” transient. In general, the chip operation should not depend on the behavior PLL output clock until the PLL is completely locked.
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