For a multibit design, is there a way to array pins or wires?
• When placing 16 bits of A for example. Name your pin A<0:15> and check the bus expansion option on the “Create pin” dialog box. Now, when you click to place a pin you will get A<0>, the next time you click the pin will read A<1> etc. Note that if two wires have the same label (or the same name as a pin) they are considered connected • Why does my t-gate LVS fail? • FETS are 4-terminal devices (source, gate, drain, bulk). The symbol used in cadence to represent a fet hides the bulk connection but still wires it to vdd or gnd (these are the well and substrate connections in your layout). Make sure your schematic has “vdd!” and “gnd!” terminals (just like any other gate) though you leave them unconnected. Make sure your layout has well and substrate connections to vdd! and gnd! • What are file locking errors? • Cadence uses lock files to prevent multiple users from modifying a cell at the same time or to prevent you from modifying a cell from multiple locations. Sometimes if Cadence cra
