Floorplanning with only usage estimates. Is it possible?
76832: 04/12/13: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO 76844: 04/12/14: Re: Newbie question: fitting in cpld 76879: 04/12/15: Re: Linking FPGAs with RocketIOs 76962: 04/12/17: Re: Inferring SRLs with INIT value 77016: 04/12/20: Re: Using low-core-voltage devices in industrial applications 77096: 04/12/22: Re: MAP failes after inserting ILA and ICON cores to the design 77114: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design 77213: 04/12/30: Re: Rocket I/O Fail modes/problems help 77235: 04/12/31: Re: Newbie looking for multiported-RAM to interface to a Spartan-III 77243: 05/01/01: Re: Altera NIOS II/Stratix II vs Xilinx Products 77304: 05/01/04: Re: code fragment causes error during bitstream generation… ISE 6.