Flip Flop problem (asynchronous or synchronous????
117838: 07/04/11: Re: Xilinx WebCase support 117844: 07/04/11: Re: Xilinx WebCase support 117852: 07/04/11: Re: Xilinx WebCase support 117897: 07/04/12: Re: spartan 3e availability 117921: 07/04/13: Re: spartan 3e availability 117943: 07/04/13: Re: Distributor stock (was Re: spartan 3e availability) 118193: 07/04/19: Re: Summer with fpgas 118208: 07/04/19: Re: Summer with fpgas 118209: 07/04/19: Re: Spartan 3 IOSTANDARD vs VCCO 118213: 07/04/19: Re: Question about reset signal for several DCMs in EDK design. 118215: 07/04/19: Re: Summer with fpgas 118303: 07/04/23: Re: Non-intrusive readback on FPGA configuration data 118304: 07/04/23: Re: Non-intrusive readback on FPGA configuration data 118316: 07/04/23: Re: V5 GTP question 118320: 07/04/23: Re: I/O-Standards: HSTL vs. SSTL and others… 118321: 07/04/23: Re: Ouputs during startup and Programming 118345: 07/04/24: Re: V5 GTP question 118482: 07/04/27: Re: Problem cascading 2 DCMs 124904: 07/10/10: Re: Need suggestion on FPGA kit Aust