Elastix uses matched delays to design the Elastic Clocks. What are the required delay margins to guarantee a correct behavior under PVT variations?
The matched delays determine the frequency of the Elastic Clocks. However, unlike synchronous circuits, the frequency of an Elastic Clock changes accordingly to the operating conditions (voltage, temperature). Given that the variability of the Elastic Clocks is highly correlated with the variability of the logic in the circuit, the required delay margins must be calculated assuming that the operating conditions for the clocks are similar to those of the logic. For a safe operation under variability, the matched delays must be longer than the delays in the logic. To define these margins, Elastix uses the same timing analysis tools than for the design of synchronous circuits. Traditionally, timing analysis was performed using two corners (best and worst). With the increase of variability, more accurate approaches considering on-chip variability (OCV) have emerged. Several vendors are supporting multi-corner OCV in their analysis tools. Recently, statistical timing analysis has also been
