edge synthesizable D flip-flop – any pitfalls?
100414: 06/04/08: Re: Compiler to FPSLIC 100484: 06/04/10: Re: How to handle the high fanout 101437: 06/05/01: Re: Question about the ip I developed 101710: 06/05/05: Re: RFID chip has battary in it or not 101828: 06/05/07: Re: flashing a led 102328: 06/05/15: Re: difference of variable and signal 104216: 06/06/21: Re: xst can, but vcomp can’t 104282: 06/06/22: Re: xst can, but vcomp can’t 104316: 06/06/23: Re: xst can, but vcomp can’t 104317: 06/06/23: Re: stimulus for FPGA 104340: 06/06/24: Re: stimulus for FPGA 105090: 06/07/13: Re: how to implement multi-port memory 105677: 06/07/28: Re: Verilog case statements 105681: 06/07/28: Re: Verilog case statements 105711: 06/07/29: Re: Verilog case statements 105712: 06/07/29: Re: “This design element is inferred rather than instantiated” (newbie) 105770: 06/07/31: Re: Verilog case statements 105899: 06/08/02: Re: generating sine-like waveforms 106011