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ECL IO to Virtex or APEX ?

APEX ECL IO Virtex
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ECL IO to Virtex or APEX ?

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17637: 99/08/17: Re: looking for info on programing XILINX 4000 series 17667: 99/08/22: Re: input offset constraint to Xilinx IOB’s 17670: 99/08/22: Re: Smallest Configurator for Xilinx 17671: 99/08/22: Re: Smallest Configurator for Xilinx 17854: 99/09/14: Re: PROBLEMS WITH ORCA 18133: 99/10/02: Re: Fineline BGAs 18439: 99/10/24: Re: xilinx foundation: bit_gen warning becasue of pullUps 18503: 99/10/27: Re: schematics ==> www 18509: 99/10/28: Re: Hold times for Xilinx FPGAs 18534: 99/10/28: Re: Hold times for Xilinx FPGAs 18562: 99/10/31: Re: Xilinx TPSYNC constraint 18606: 99/11/02: Re: StateCAD versus Viewdraw 18630: 99/11/04: Re: Input metastability 18658: 99/11/05: Re: Input metastability 18659

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