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During a passive release, is CPU-PCI write posting disabled?

April 26, 2017disabled passive posting release write

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During a passive release, is CPU-PCI write posting disabled?

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Posting of CPU to PCI writes is disabled from the time the passive release is initiated (toggling of PHLD#) until the active release is generated by the PIIX3 (holding PHLD# deasserted for at least 2 clock cycles). This active release indicates the end of the ISA transfer. This disabling is necessary to prevent deadlock scenarios.