Does the LMB bus support custom IPs?
It seems like the LMB bus does not support custom IP’s in 8.2 version. Question 6. I’m using the expanded I/O header with an SPI interface core. I’ve configured the voltage outputs for LVTTL which is a 3.3V standard but I’m finding I only get 2.5V for a high. The VCCO for the expanded I/O pins does get 3.3V (at least according to the documentation). So what am I missing in order to get a 3.3V output? Answer: The translation to 2.5V appears to be occurring as a result of the transistor bus switch. The FPGA does output 3.3V which then becomes 2.5V on the other side of the switch. According to the bus switch datasheet for a 5V signal there is about a 1V loss across the switch. Question 7. I’m using the expanded I/O header with an SPI interface core. I’ve configured the voltage outputs for LVTTL which is a 3.3V standard but I’m finding I only get 2.5V for a high. The VCCO for the expanded I/O pins does get 3.3V (at least according to the documentation). So what am I missing in order to get
