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Does the debugging feature of a SX Chip always need the ~150 instruction space at the last bank, or is this less or not needed depending on the tool vendor?

April 26, 2017Bank chip debugging depending feature instruction needed sx

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Does the debugging feature of a SX Chip always need the ~150 instruction space at the last bank, or is this less or not needed depending on the tool vendor?

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This space is needed when debugging to hold the debug kernel code in any of the SX tools. Our newest chips, the IP2022 do not require this overhead, by benefit of a new debug architecture.