does ISE 6.3 improve timing vs. ISE 6.2 ?
74420: 04/10/11: Re: Interfacing an 1GS ADC 75321: 04/11/02: Re: XST: suppressing incorrect optimizations in VHDL code 74338: 04/10/08: Re: Interfacing an 1GS ADC 74570: 04/10/14: Re: GLKP and GLKS 75425: 04/11/05: Re: Xilinx Maximum output required time after clock 75457: 04/11/06: Re: IO Timing constraints with internal clocks 75581: 04/11/10: Re: Overshoot/undershoot towards 2V4000 75610: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems 75726: 04/11/13: Re: Spartan3 Block RAM from WebPACK 76223: 04/11/29: Re: XST question 76476: 04/12/03: Re: making an fpga hot 76497: 04/12/04: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO 76609: 04/12/07: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO 76704: 04/12/09: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO 76756