Does FRAM have the same problem with scalability as EEPROM?
Unlike FRAM, EEPROM employs a floating gate charge storage design which necessitates high voltage and costly, power-hungry and space-hogging circuits, such as transistors and charge pumps. A restriction of all this high-voltage legacy circuitry is that it does not easily scale to smaller and smaller IC process node manufacturing. TI’s advanced 130 nanometer (nm) FRAM manufacturing process results in chips that are much smaller than the 180 – 220 nm node sizes used by in most EEPROM-based contactless smart ICs, giving FRAM products a significant advantage in size, performance, and power efficiency. Further, the FRAM manufacturing process is fully compatible with digital CMOS processes making the technology easy to scale to smaller technology nodes in the future.
