Does Eldo RF support Verilog-A?
A – Yes. Eldo RF analyses (SST and MODSST) are compatible with Verilog-A, which means you can simulate circuits described with a mix of plain transistor-level blocks and Verilog-A ‘modules’ (the ‘module’ is the basic Verilog-A design unit). This option provides a solution for those customers looking for a way to speed-up simulations by using behavioral models instead of detailed transistor-level models for all or part of their circuits. This also allows ‘system-level’ simulations, where all circuit blocks are defined using Verilog-A models. Not all Verilog-A statements are compatible with the Eldo RF analyses (basically the statements which create (or test for) ‘events’ – Verilog-A includes the notion of event, even though this is an analog language – are not supported. The ddt() and idt() operators (time-derivatives) are fully supported, and also the Laplace blocks for easy implementation of filters. The noise functions are also supported. Using Verilog-A with Eldo RF requires a Veril
