Can the Virtex series of FPGAs support dynamic reconfiguration?
A Yes, except for the Block SelectRAMs. The configuration logic is separate from the user logic and does not require use of normal resources allowing for continued operation of sections that do not change. The configuration write sequence is a glitchless operation, so that only the memory bits that were modified are toggled. The one exception to this is the Block SelectRAM. Implementing a third read/write port for the RAM cells specifically for configuration would have been too costly in terms of area and RAM performance. The configuration logic requires the use of the read/write ports of the Block SelectRAMs when the memory contents must be read or written.
