Can the aJ-100 access more than 32MBytes of address space?
The aJ-100 address, A[27:0], supports a total address space of 256MBytes. A27=1 is reserved for internal use leaving 128MBytes for external use. The aJ-100 decodes A[24:22] for the chip select outputs, CS7-CS0, which are also qualified with A[27:25]=000. The 8 chip selects therefore each decode 4MBytes of address space and cover a total address space of 32MBytes. Each chip select configuration register defines the timing used for a transaction in the address space for which that chip select applies. For addresses above the low 32MB, the timing is repeated in each 32MB block. That is, the timing select mechanism uses the A[24:22] decode but ignores A[27:25]. If the following issues seem too troublesome, one simple alternative is to use only 12MB of one or both types of memory freeing up one or two chip selects for peripherals. Read more…
