Can my design be operated at a power supply voltage greater than the voltage specified by the foundry as long as the voltage is less than junction breakdown?
Failure to operate a design within the voltage limits specified by the foundry will result in significant risk of early failure caused by either Time Dependent Dielectric Breakdown (TDDB) or Hot Carrier Damage (HCD). HCD will have the most rapid measurable effect, which leads to a shift in transistor electrical characteristics that may cause circuits to fail. TDDB is the catastrophic failure of gate oxide that will lead to a non-functional transistor. It is advisable not to exceed recommended power supply voltage limits and any attempt to use higher than recommended voltage will be at the designer’s risk. Further discussion on CMOS failure mechanisms can be found in a short tutorial on Reliability in CMOS IC Design. 13.0 Can the current limits for metal interconnect in the design rules be exceeded if the design is only a proof of concept prototype? Current density limits, specified in the design rules, are defined by foundries to provide reasonable assurance that metal interconnects wi
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