Can multiple Nios II processor cores be implemented in a single FPGA?
A. Yes, many developers implement multiple Nios II processors on a single FPGA. Altera’s SOPC Builder system design software provides a drag-and-drop interface to add and connect multiple processors, shared memories, and hardware mutex and mailbox peripherals. The Nios II processor EDS supports software development and debug of multi-CPU designs. Several embedded partners also provide RTOS and debugging tools to enhance development of multi-CPU designs.
