Can L-Edit do lateral parasitic extraction, for example, between 2 Metal1 traces?
Currently, L-Edit does not support lateral parasitic extraction. However our HiPer PX product scheduled to release early 2008 will have the capability to extract hierarchical 3D resistance and capacitance (RC) values for their analog and mixed-signal design chip layout. Accurate modeling of parasitics occurring both across metal layers and between the metal layers and the chip substrate will be some of the features of HiPer PX.