Can ISE text editor generate CRLF line endings?
EDK Simulation: 89568: 05/09/19: Simulation : EDK EDM: 21473: 00/03/23: FPGA & single point failure 21631: 00/03/27: Re: FPGA & single point failure Edmond Tam: 7728: 97/10/07: Design verification jobs Edoardo: 40267: 02/03/04: Re: negative offset warning message 47794: 02/10/04: Re: modelsim XE starter 47795