Can all functions and structures be used inside the SCTL?
No. Functions that take longer than one tick, such as analog I/O functions or any functions that wait cannot be used inside the SCTL. Also, if you have a chain of logic inside the loop that takes longer than one clock tick to execute, this logic cannot be used inside the SCTL and your VI will fail to compile. Sequence Structures may be placed within the SCTL, but will be removed from the code before it executes on the FPGA. Here is a list of some functions that cannot be used in a SCTL. Please refer to the LabVIEW Help for more information about SCTL support and timing information for individual VIs.
