bottom up synthesis with synplicity?
38804: 02/01/25: Re: Intel vs. AMD 38844: 02/01/26: Re: Xilinx webpack 38845: 02/01/26: Re: Xlx simprim library 38876: 02/01/27: Re: Coregen Half-Band FIR filter implemenation does not work 38877: 02/01/27: Re: Xilinx webpack 38883: 02/01/27: Re: Xilinx webpack 38967: 02/01/29: Re: Xilinx webpack 39073: 02/01/31: Re: glitchless clock enable/disable in spartanII 39074: 02/01/31: Re: The LUT puzzle, Iam on the way 39117: 02/02/01: Re: the cause of the simulation/synthesis mismatch 39119: 02/02/01: Re: glitchless clock enable/disable in spartanII 39157: 02/02/02: Re: glitchless clock enable/disable in spartanII 39233: 02/02/04: Re: solutions manuals, and no they are not for school 39300: 02/02/06: Re: Virtex-II and SDRAM Controller at 133MHz 39301: 02/02/06: Re: FPGA vs GAL : Lattice Its a TROLL 39332: 02/02/06: Re: FPGA vs GAL : Lattice 39346: 02/02/07: Re: Virtex-II and SDRAM Controller at 133MHz 39391: 02/02/08: Re: FPGA vs GAL : Lattice 39406: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4