At reading the data register to clear the UART reception interrupt flag before standby processing, a delay interrupt occurs sometimes. What is the cause?
• Answer :A possible cause is that UART reception interrupt flag clear processing exists in the main routine and the UART reception interrupt is enabled. When these settings are implemented at the same time, an internal conflict that causes an interrupt source to be cleared according to the timing of interrupt processing occurs in the CPU. In this case, the CPU switches to a delay interrupt with the largest interrupt number. To avoid this symptom, take countermeasures such as disabling the UART reception interrupt before clearing the UART reception interrupt flag.
