Asynchronous signals recommendations?
Mike Nicklas: 66615: 04/02/24: Driving INOUT signals 66680: 04/02/25: Re: Driving INOUT signals 66691: 04/02/25: Re: Driving INOUT signals 66934: 04/03/01: Re: Driving INOUT signals 67323: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files 67324: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files 67350: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files 67397: 04/03/11: Re: Xilinx ISE 6.1, .mcs prom files Mike Oxlarge: 93802: 05/12/30: Newbie question – using library “design elements” 93816: 05/12/31: Re: Newbie question – using library “design elements” 93960: 06/01/03: Using posedge and negedge causing me grief 93962: 06/01/03: Re: Using posedge and negedge causing me grief 94022: 06/01/04: Re: Using posedge and negedge causing me grief 94209: 06/01/07: Re: Using posedge and negedge causing me grief Mike Palmer: 9329: 98/03/06: Re: The case for free operating systems and EDA Mike Panson: 10575: 98/06/02: BiPolar Prom 2 PLD 10583: 98/06/03: Re: Xilinx Foundation Mike Peattie: 13876