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Aren VHDL and Verilog models too slow to be usefull?

April 26, 2017models slow usefull verilog vhdl

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Aren VHDL and Verilog models too slow to be usefull?

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No, not if they are written at a high enough level of abstraction. Models written at the register transfer level (RTL) may be too slow but, behavioral models are fast enough for hardware verification.