Are there any prerequisites for using Calibre xRC?
A. GDSII layout database and process technology information are required. The process information can take the form of parasitic data tables, dielectric constants, permitivities et al, or even an existing LPE file from a competitive tool. Q. What are your future plans for Calibre xRC? A. In the product area, we are developing a new engine for full-chip extraction that will provide improved high-speed performance with the accuracy of flat-type extraction. The thrust of further research and development will be towards performance scaling and design optimization. Performance scaling will occur with the parallel processing of multiple FDBs, and design optimization will be a move towards predicting the behavior of interconnect, rather than post-layout analysis of its effects. This will be enabled by the incorporation of Design for Manufacturability technology.
