Are there any alignment/size constraints on RingIO buffers allocated from POOL?
On C4x based devices, RingIO data buffer and attribute buffer must be aligned to the L2 cache line boundary for the DSP, i.e. 128 bytes. This is applicable to all buffers allocated from POOL. So RingIO buffer size (data buffer + foot-buffer), and attribute buffer size must be a multiple of 128 bytes.
