Are there any alignment restrictions on POOL buffer sizes?
Yes. POOL buffers must be cache-line size aligned for devices such as TI C64x (128 bytes L2 cache line size for Davinci, DM6437 etc.) This is needed since each buffer must start on a cache-line boundary. In addition, the full POOL size as configured in DSPLink dynamic configuration must also be a multiple of cache-line size to ensure that all DSPLink control structures remain aligned to cache-line boundaries.
