Are POOL buffers on DSP-side in cached memory?
Yes, the DSPLINKMEM/DSPLINKMEM1 segments into which the POOL is placed are cacheable on the DSP-side. The control for enabling/disabling cache is with the system integrator through DSP/BIOS configuration. DSPLink maintains cache coherence on DSP-side for all its modules control structures, as well as POOL buffers if they are sent using DSPLink modules such as MSGQ (message buffer cache coherence is performed), CHNL (data transfer cache coherence is performed), NOTIFY (payload cache coherence is performed) and RingIO (data and attribute buffer cache coherence is performed). For protocols which use ListMP and PROC_read/PROC_write in the applications, cache coherency of POOL buffers needs to be done by the application.
