Are FPGAs available with ADCs onchip ?
112825: 06/11/29: Re: DVI clock generation 112845: 06/11/29: Re: FPGA application field 112885: 06/11/30: Re: DVI clock generation 112891: 06/11/30: Re: FPGA application field 112903: 06/11/30: Re: DCM jitter (again) 112933: 06/12/01: Re: DCM jitter (again) 113175: 06/12/07: Re: Spartan-3A launched 113217: 06/12/08: Re: About partial reconfiguration in Virtex 4 113433: 06/12/13: Re: BLVDS_25 @ SPARTAN3 113530: 06/12/15: Re: electrical level conversion 113536: 06/12/15: Re: electrical level conversion 113544: 06/12/15: Re: 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4 113547: 06/12/15: Re: Xilinx PMCD+DCM reset question… 113629: 06/12/18: Re: electrical level conversion 113633: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM 113637: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM 113743: 06/12/20: Re: CCLK Virtex4 IBIS model. 113750: 06/12/20: Re: CCLK Virtex4 IBIS model.