Any example on how to use the audio codec?
Two VHDL examples provided by: * Xess, Inc.: Audio Loopback in VHDL * University of Queensland: Description and Sources 6.3.2 – Suppose I have a 4-bit signal, continuously updated, which I want to feed to a DAC (4bit,16steps of output voltage) which drives a speaker. The audio DAC takes a 16-bit sample in serial at certain sampling frequency. You can map your 4-bit sample to a 16-bit sample to drive the audio DAC. 6.3.3 – I would need about 4 or 5 of these DAC’s, as I have 4 or 5 4 bit signals to drive speakers. You can certainly combine (sum) these output signals sample by sample (if they are output at the same frequency) and then map the result to a 16-bit sample to the on-board DAC. 6.3.4 – I am a bit confused on how to actually instantiate this codec now and run my timing sim with my module, feeding the codec(and spkr), since the example is VHDL and seems to be looping to memory and the codec datasheet doesnt give Verilog implementation advice. The VHDL loopback example can show yo
