A VHDL design can be moved to any tool or technology. Right?
On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes sythesisable code, but may interpret that code in different ways. This is particularly an issue for us at Doulos in developing our training courses, because we like to present a reasonably generic approach to writing VHDL for synthesis. This means that the VHDL we teach you is guaranteed to be more transportable between synthesis tools than it otherwise would be. Our pain is your gain! In addition, because we are so aware of the differences between synthesis tools this means that we emphasise the best way of writing VHDL to get the best from your synthesis tool. For FPGA, code that uses on
