PLD in small package ??
2181: 95/10/27: Re: Xilinx Configuration Memory Hacking 2194: 95/10/30: Re: Xilinx Configuration Memory Hacking 2255: 95/11/10: Re: Xilinx Configuration Memory Hacking 3267: 96/05/07: Re: Simple Xilinx board 3286: 96/05/09: Re: On FPGAs as PC coprocessors [rererepost] 3681: 96/07/12: Xilinx reconfigurable logic strategy 3836: 96/08/08: Re: “Xilinx nixes its antifuse arrays” 3933: 96/08/22: Re: XC6200 FPGAs 4289: 96/10/10: FPGA Web Links William Jones: 10001: 98/04/21: C++, C, Java to hardware compiler William K. McFadden: 916: 95/03/29: Re: Excuse me while I vent about Data I/O & Abel… William Killian: 24677: 00/08/16: Re: Non-disclosures in job interviews William L Hunter Jr: 3291: 96/05/09: Re: Simple Xilinx board 36022: 01/10/26: ILA CHIPSCOPE 36847: 01/11/22: Re: Decoupling capacitors on Virtex II 41462: 02/03/29: Re: HELP me, about chipscope analyzer 42156: 02/04/17: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01 42180: 02/04/18: Re: GND Outputs being opti