What is failsafe?
Failsafe is a feature of an LVDS receiver that ensures a known state of its outputs in cases when a fault condition occurs. National Semiconductors LVDS receivers may provide failsafe support for open, shorted and terminated LVDS inputs. When the failsafe circuitry detects any of these fault conditions, it sets the LVDS non-inverting output pin (OUT+) to a static HIGH (typically 1.4 V for LVDS), and its complement, inverting output pin (OUT-), to a static LOW (typically 1.0 V for LVDS) voltage level. This is a +400 mV differential signal. Some devices may also have a loss-of-signal (LOS) reporting pin available. In this case, when a fault condition occurs, the device sets the LOS pin to a logic LOW level to inform that a failsafe condition of the line is present and that the LVDS outputs are placed into the failsafe mode. The following describes typical faulty cases at the input of a receiver and the receiver response to fault condition. • Open Input Failsafe When the receiver inputs a
