What Is Core Prefetch?
A fundamental problem with increasing DRAM bandwidth is increasing the data transfer rate between the DRAM interface and the DRAM core. One possibility is to increase the frequency of the DRAM core to match that of the DRAM interface. However, this introduces additional circuit complexity, increases die size, and raises DRAM power consumption, resulting in higher manufacturing cost and lower yield. Core prefetch takes a different approach to solving this problem by allowing the DRAM core to run at a reduced speed compared to the DRAM interface. To match the bandwidth of the interface, each core access transfers multiple bits of data from the core to make up for this difference in transfer speeds. In this manner, core prefetch lets DRAM bandwidth increase, even if the DRAM core is limited to operating at a lower speed. Figure 3 illustrates that core prefetch has become a widely adopted method for improving interface signaling rates of modern DRAMs; this preserves high-volume manufactura
