What is pipeline burst SRAM (PB SRAM)?
Pipeline burst SRAM uses pipelining techniques to execute SRAM requests in parallel, speeding up multiple accesses to the SRAM modules and removing some of the burden on the bus. What is the difference between interleaved and linear burst modes? When bursting SRAM goes to access data, it includes logic to allow it to cycle through the addresses by itself without any help from the CPU. Intel machines require that this addressing be “interleaved” (i.e., access addresses 0, 2, 4, 6, … on the first pass and 1, 3, 5, 7, … on the second pass). PowerPC and other machines require that this addressing be “linear” (i.e., access addresses 0, 1, 2, 3, …). What is this “2-1-1-1” notation I keep seeing? This refers to the number of clock cycles which “bursting” cache requires to access data. It’s often listed in formats such as “2-1-1-1” or “3-2-2-2”. The first number indicates the number of clock cycles required to deliver the first data chunk, the second indicates the number of clock cycles
