What is Multi cycle path?
They are the paths that intentionally require more than one clock cycle to become stable. Therefore, they require special multi-cycle setup and hold time calculations. Declaring the multi-cycle path tells the tool to adjust its measurements so it doesn’t incorrectly report timing violations. RTL vs Gate level timing: RTL code, models a logic function without regard to its implementation, whereas gate level code specifies the exact gates required. For example, consider the code for both the cases: RTL Code: assign out = ((a&b) | !a); Gate level code : and (s2, a, b); not(s1, a); or(out, s1, s2); Modeling delays at the gate level is straight forward. The delay of each gate is found in the tech. library. However, manually implementing HDL code with delays for each gate is time consuming. At the pre-layout state, most design methodologies use synthesis to provide a gate model with delays.
