How far can the device mutliply up or divide down by?
• The device has two (one for the reference clock and another for feedback clock) internal 10 bit pre-dividers for the PFD (Phase Frequency Detector). Additionally, it has a post divider (values are 1,2,4,8,16) for the feedback path. For PLL operation, the reference clock and feedback clock frequency (PFD update frequency) must be the same. Thus, using the pre and post dividers, a wide number of multiplication (1.33x, 1.5x, 24x, 6.144x, etc.) and division factors (0.5x, 0.75x, 0.001x, etc.) are achievable.
