What is M1?
20448: 00/02/10: Re: Timing constraint on a DLL output20615: 00/02/16: Re: Timing constraint on a DLL output25434: 00/09/11: Re: More than 4 clocks in virtex26806: 00/10/30: Re: xilinx floor planner issues37025: 01/11/28: Re: How to set timing constraint in Xilinx VirtexII device when usingKate Palmer:55909