Xilinx FPGAs with Mentor Tools?
3060: 96/03/24: Re: MTI VHDL simulation w/ Xilinx 3159: 96/04/16: Re: ACTEL design with Synopsys Robert Bauman: 7532: 97/09/19: Re: Altera Internal PLL Robert Baumgartner: 55133: 03/04/28: simulation of a ppc405 smartmodel 62417: 03/10/29: Xilinx PPC405 DCR Interface 63417: 03/11/21: Re: Memory Initialization: mif, coe, hex, etc, Robert Bernecky: 10512: 98/05/26: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)) robert bible: 6618: 97/06/05: Don’t Design With Altera Parts…