SDRAM controller ?
19764: 00/01/11: Re: XC4000 Configuration Bitstream structure 19775: 00/01/11: Re: 100 MHz counters 19803: 00/01/12: Re: Xilinx Spartan2 19804: 00/01/12: Re: 100 MHz counters 19813: 00/01/13: Re: Reliability of programming SRAM FPGAs 19825: 00/01/13: Re: Design security 19826: 00/01/13: Re: fastest 32 bit RISC 19848: 00/01/14: Re: fpga board 19849: 00/01/14: Re: DDC Core for FPGA 19862: 00/01/14: Re: fastest 32 bit RISC 19878: 00/01/15: Re: XACT & XC4000E – Need help 19888: 00/01/16: Re: Partly reprogrammable FPGAs 19889: 00/01/16: Re: XACT & XC4000E – Need help 19894: 00/01/16: Re: Random Number Generator 19895: 00/01/16: Re: timing diagrams 19899: 00/01/17: Re: Random Number Generator 19908: 00/01/17: Re: Viterbi decoder in FPGA 19909: 00/01/17: Re: Random Number Generator 19922: 00/01/18: Re: Random Number Generator 19933: 00/01/19: Re: Random Number Generator 19937: 00/01/19: Re: Need advice on timing problem 19944